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Digital DRC &
Power Consumption Analysis
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| Profil : |
Microelectronique and/or Telecommunications Engineer - minimum
2 years exp.
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Role
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For a 65nm digital chip, working as part of the digital design team the
mission consists in two main activities :
Digital and Power Management DRC:
- Build a design checker environment based on Spyglass
and CLP (Conformal Low Power) tools
- In parallel to design activities, use this flow to
extract and analyze all design and power management issues: RTL coding rules,
floating nodes, etc.
- Report and align with the design team to ensure the
design is Spyglass/CLP-clean before PG
Power Consumption Analysis:
- Build a power consumption analysis environment based on
Synopsys Primetime PX and design netlist.
- Use this flow to analyse and extract power consumption per
module for functional scenarios
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| Skills :
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- Good knowledge of digital design (power, clock, reset
management) and design RTL coding (VHDL & Verilog)
- Understanding of power contributors in digital IC design: leakage, dynamic
switching activities, etc.
- Skilled with Synopsys Primetime PX tool or equivalent tool
- Skilled with RTL & Gate simulations (Modelsim)
- Skilled with DRC tools (Spyglass, CLP)
- Environment: Linux / ClearCase / Makefile
- Scripting / programming using Perl, TC
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| Disponibilité : |
Asap |
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Place of work: | Sophia-Antipolis
- This is in South of France. Nice airport. |
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| Contrat: | Permanent |
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| Salary : | According
to educational qualificiations and experience.
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If
this offer interests you, send a letter in support of
your application and your CV at : contact@axylog.com
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