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| Profil : |
Engineer - minimum
2 years exp.
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Role
:
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Working as part of the digital design team within the Mixed-Signal Group the
mission consists of:
Implementation of high complexity digital basebands in 65 nm technology,
with low power techniques and usage of most up to date design flows
RTL synthesis with timing constraints definition
Running STA and analyzing the results
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| Skills :
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ASIC/SOC Design Flows with
experience in vhdl, synthesis, DFT and STA
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Current EDA Tools experience
especially Synopsys Design Compiler, Primetime-SI, Tetramax, Fastscan
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Environment: Linux / ClearCase
/ Makefile - Scripting / programming using Perl, TCL
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| Disponibility : |
Asap, or after your noticed
period time |
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Place : | Sophia-Antipolis
- This is in South of France. Nice airport.
We will help you in finding
place to leave with our professionnal real estate
partners. |
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| Contrat : | Permanent
or other type as freelance. |
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| Salary : | According
to educational qualificiations and experience.
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If
this offer interests you, send a letter in support of
your application and your CV at : contact@axylog.com
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