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| Profil : |
Microelectronique and/or Telecommunications Engineer - minimum
2 years exp.
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Tasks :
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- Analysis of the existing design to support the definition of the new DFT
strategy
- full or partial contribution to the development of the top-level Test
Controller module (RTL/Verilog).
- Support the synthesis team for scan insertion issue
- Generation of all required ATPG test patterns (TDL)
- Support the design team to implement PBIST/MDP in the design
- Generation of all required PBIST test patterns (TDL): GO/NOGO, repair,
retention
- Validation of the memory repair strategy
- Contribution to the development of other required TDL (DC PARA, IDDQ,
burnin)
- Full QC of test patterns doing Gate Level Simulation (Modelsim with
timing/SDF)
- Porting of all existing ATPG patterns from subchip-level at top-level
- From silicon-out, support test engineers for TDL debug (tester debug and
pattern regeneration).
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| Skills :
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- Strong experience of ATPG flow and scan pattern compression
methodologies (Mentor TestKompress and/or Synopsys DFT Compiler Max) OR
Strong experience of Memory BIST flow. Good knowledge of TI Memory BIST flow
is better.
- Knowledge of scan insertion methodology using Synopsys DC Compiler
- RTL design of a digital module using Verilog language (VHDL nice to have)
- Knowledge on power management for a digital IC
- Experience of RTL and gate (with timings) simulation /debug using Modelsim
- Scripting / programming using Perl and TCL
- Knowledge of IEEE 1149.1 and 1500 standard
- Environment: Linux / ClearCase / Makefile / TI FLOW3
- English: high-level required (multisite project: Israel, Dallas)
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| Disponibilité : |
Asap |
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Place of work: | Sophia-Antipolis
- This is in South of France. Nice airport. |
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| Contrat: | Permanent |
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| Salary : | According
to educational qualificiations and experience.
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If
this offer interests you, send a letter in support of
your application and your CV at : contact@axylog.com
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